This patent application claims priority from Japanese patent application No. 2000-131174 filed on Apr. 28, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus for testing a semiconductor device. In particular, the present invention relates to a semiconductor device testing apparatus that does not interrupt a test just after restarting of the test and also does not apply an input-signal pattern to the semiconductor device, which causes a match-fail, until the end of the test.
2. Description of the Related Art
FIG. 1 is a block diagram that shows a configuration of a pattern generator 10 of a conventional semiconductor device testing apparatus. The pattern generator 10 has a match-fail detecting unit 20, a sequence control unit 40, and a pattern data memory 50. A control apparatus 210 controls each unit of the pattern generator 10. Each unit of the pattern generator 10 receives a clock signal that is output from a reference clock generator 60.
The semiconductor device testing apparatus is used for testing a logic IC such as a system LSI. In particular, the semiconductor device testing apparatus 100 can test a plurality of semiconductor devices at the same time. The pattern generator 10 generates an input-signal pattern 12 and an expectation value signal pattern 14 according to the predetermined control sequence. The input-signal pattern 12 is a signal to be input to a semiconductor device that is an object to be tested. The expectation value signal pattern 14 is a signal to be output from the semiconductor device when the input-signal pattern 12 is applied to the semiconductor device.
The pattern data memory 50 stores data of the input-signal pattern 12 and the expectation value signal pattern 14. The sequence control unit 40 outputs an address signal 45 to the pattern data memory 50 so that the pattern data memory 50 generates the input-signal pattern 12 and the expectation value signal pattern 14. The sequence control unit 40 receives a match signal 96 from the match signal generator 94. The match signal 96 shows whether the output-signal pattern, which is output from the semiconductor device when the input-signal pattern 12 is applied to the semiconductor device, becomes the predetermined value that is determined based on the expectation value signal pattern 14. The match-fail detecting unit 20 outputs a match-fail signal 22 to the sequence control unit 40 when the match-fail detecting unit 20 has not received a match signal 96 during a match cycle while waiting for the match signal 96.
The sequence control unit 40 includes a pattern counter 42, an address counter 44, and a controller 46. The pattern counter 42 counts match cycles. The address counter 44 counts addresses of control sequences. The controller 46 controls the pattern counter 42 and the address counter 44 according to the predetermined control sequence. The controller 46 also outputs a match cycle signal 43 to the match-fail detecting unit 20. The match cycle signal informs the match-fail detecting unit 20 that the matching process is being processed. The controller 46 further outputs a clock control signal 48 to the reference clock generator 60 to stop generation of a clock signal when the controller 46 receives a match-fail signal 22 from the match-fail detecting unit 20. The clock control signal 48 controls the reference clock generator 60 to stop generating a clock signal.
The controller 46 controls the pattern counter 42 and the address counter 44 in order to continue the control sequence when the controller 46 receives the match signal 96 during the match cycle. On the other hand, if the controller 46 receives the match-fail signal 22, the controller 46 controls the pattern counter 42 and the address counter 44 in order to stop the control sequence, and the controller 46 executes a fail stop process that outputs the clock control signal 48. The fail stop process stops a test. The test has to be started over again to restart the testing.
When a plurality of semiconductor devices are tested at the same time, a test is performed while confirming whether the writing of the input-signal pattern 12 to all the semiconductor devices and reading of the output-signal pattern from all the semiconductor devices have been finished normally. Thus, a series of tests are divided into several steps, and whether the reading and writing process of each semiconductor devices 200 has been finished is confirmed during a match cycle. The match cycle is a predetermined time period between each step of the series of tests. If the reading and writing process of each semiconductor device 200 has not been finished during the match cycle, it is found that there is a defective device within any one of a plurality of semiconductor devices. After the test is stopped, the defective device is removed from the test object, and then the test is restarted.
FIG. 2 is a flow chart that shows a process for testing one semiconductor device using a conventional semiconductor device testing apparatus. The input-signal pattern 12 is applied to a semiconductor device at test 1 (S102). Then, if the output-signal pattern output from the semiconductor device matches the predetermined value that is determined based on the expectation value signal pattern 14 during the match cycle (S104), a test 2 (S106) is performed continuously. However, if the output-signal pattern output from the semiconductor device does not match the predetermined value that is determined based on the expectation value signal pattern 14 during the match cycle (S104), the test finishes at that point as match-fail. Then, the same process is performed at a match cycle (S108) after the test 2 (S106). If the test 3 (S110) is finished, all the processes of testing have been finished.
FIG. 3 is a flow chart that shows a process for testing a plurality of semiconductor devices at the same time using a conventional semiconductor device testing apparatus. As shown in FIG. 3, if the output-signal pattern output from the semiconductor device matches the predetermined value during the match cycle (S154, yes) after the test 1 (S152) is performed, a test 2 (S156) is performed continuously.
However, if the output-signal pattern output from the semiconductor device does not match the predetermined value during the match cycle (S154, no) after the test 1 (S152) is performed, the test is stopped at that point as match-fail (S162). To test the other devices continuously after removing the semiconductor device that causes the match-fail from the test object after stopping the test (S164), the test 1 (S152) is performed again from the beginning. If the test does not continue, the test ends at that point.
After the test 2 (S156) has been performed, the same process using the process of the match cycle (S154) is performed at the match cycle (S158). If the output-signal pattern output from the semiconductor device does not match the predetermined value during the match cycle (S158, no) after the test 2 (S156) is performed, the test is stopped at that point as match-fail (S162). To test the other devices continuously after removing the semiconductor device that causes the match-fail from the test object after stopping the test (S164), the test 1 (S152) is performed again from the beginning. If the test does not continue, the test ends at that point. If the test 3 (S160) is finished, all the processes of the test end.
FIG. 4 is a time chart that shows a process for testing a plurality of semiconductor devices at the same time using a conventional semiconductor device testing apparatus. As shown in FIG. 4, a plurality of semiconductor devices are tested to see whether the output-signal pattern output from the semiconductor device matches the predetermined value during a match cycle (S204) after performing a test 1 (S202).
Here, the test for all the devices is stopped when any one of the semiconductor devices causes match-fail (S206). Then, the semiconductor device that causes the match-fail is removed from the test object (S208). Then, the test starts again from the test 1 (S210) for the other remaining semiconductor devices. Then, the test 1 (S210), a test 2 (S214), and a test 3 (S218) are performed successively, and if the match-fail does not occur at each of the match cycles (S212, S216), all the processes of the test end.
Conventionally, when a plurality of semiconductor devices are tested at the same time, and if the match-fail occurs for one of the semiconductor devices during the match cycle, the test for all the semiconductor devices is stopped, and then the semiconductor device that causes the match-fail is removed from the test object. Moreover, to finish the test for the remaining semiconductor devices, the test should be started again from the beginning. Thus, the object of reducing the whole testing time by testing a plurality of semiconductor devices at the same time cannot be achieved by the apparatus and the method described above.
Furthermore, in a case of testing a system LSI that contains a built-in flush memory, and if the test is restarted from the beginning after the test is stopped halfway by the match-fail, the data may be written into the flush memory excessively so as to destroy the flush memory because the same data is written into the flush memory repeatedly. Thus, the test cannot be performed in the result.
Furthermore, in a case of testing a system LSI that contains a built-in phase lock loop device (PLL device), a clock has to be applied to the system LSI continuously for a period of time in order to lock the PLL prior to the start of the test. Therefore, to restart the test for the remaining semiconductor devices after the test is stopped because of the match-fail, we have to wait until the PLL is locked each time for restarting the test. Therefore, the test cannot be started immediately.
Therefore, it is an object of the present invention to provide a semiconductor device testing apparatus and method for testing semiconductor device, which is capable of overcoming the above drawbacks accompanying the conventional art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a test signal supplying apparatus for a semiconductor device testing apparatus that tests a plurality of semiconductor devices comprises: a test pattern generating unit for outputting an input signal pattern to the semiconductor devices and receiving a match signal which indicates the semiconductor device, to which the input signal pattern is applied, is passed in the test; and a match-fail detecting unit for receiving the match signal to detect a semiconductor device that fails in the test and outputting a match-fail signal for identifying the semiconductor device that fails in the test; and a stop signal output unit connected to the match-fail detecting unit for receiving the match-fail signal from the match-fail detecting unit, storing the match-fail signal, and outputting a first stop signal that stops an application of the input signal pattern to the semiconductor devices that fail in the test identified by the stored match-fail signal.
The stop signal output unit may further output a second stop signal that stops application of the input signal pattern to the semiconductor devices that passes the test indicated by the match signal. The stop signal output unit may have a register connected to the match-fail detecting unit for receiving the match-fail signal from the match-fail detecting unit and storing the match-fail signal.
The stop signal output unit may further have a logical addition circuit connected to the register for receiving the match signal and the match-fail signal stored in the register to output the first stop signal or the second stop signal. The stop signal output unit may output the second stop signal during a predetermined cycle; and the test pattern generating unit may restart the application of the input signal pattern to the semiconductor devices after the end of the predetermined cycle.
The stop signal output unit may output the first stop signal until the end of the test. The stop signal output unit may output the second stop signal during a predetermined cycle; and the test pattern generating unit may output the input signal pattern after the end of the predetermined cycle.
According to the second aspect of the present invention, a semiconductor device testing apparatus for testing a plurality of semiconductor devices; comprises: a test pattern generating unit for outputting an input signal pattern to the semiconductor devices and outputting an expectation value signal pattern, which is expected to be output from the semiconductor device when the input signal pattern is applied to the semiconductor device; a comparator that compares an output signal patterns, which are output from the plurality of semiconductor devices, and a predetermined value determined based on the expectation value signal pattern and outputs a match signal when the output signal patterns match the predetermined value; a match-fail detecting unit for receiving the match signal to detect a semiconductor device, the output signal pattern of which does not match the predetermined value, and outputting a match-fail signal for identifying the semiconductor device, the output signal pattern of which does not match the predetermined value; and a stop signal output unit connected to the match-fail detecting unit for receiving the match-fail signal from the match-fail detecting unit, storing the match-fail signal, and outputting a first stop signal that stops application of the input signal pattern to the semiconductor devices, the output signal patterns of which does not match the predetermined value, identified by the stored match-fail signal.
The stop signal output unit may further output a second stop signal that stops application of the input signal pattern to the semiconductor devices, the output signal patterns of which matches the predetermined value. The stop signal output unit may have a register connected to the match-fail detecting unit for receiving the match-fail signal from the match-fail detecting unit and storing the match-fail signal.
The stop signal output unit may further have a logical addition circuit connected to the register for receiving the match signal and the match-fail signal stored in the register to output the first stop signal or the second stop signal. The semiconductor device testing apparatus may further comprise a waveform formatter connected to said test pattern generating unit and said stop signal output unit for receiving said input signal pattern from said test pattern generating unit, receiving the first stop signal or the second stop signal from the stop signal output unit, formatting and outputting the input signal pattern except when receiving the first stop signal or the second stop signal.
The waveform formatter may output the input signal pattern except when the waveform formatter receives the first stop signal until the end of the test. The stop signal output unit may output the second stop signal during a predetermined cycle; and the test pattern generating unit may output the input signal pattern to the waveform formatter after the end of the predetermined cycle.
According to the third aspect of the present invention, a method for testing a plurality of semiconductor devices; comprise: outputting an input signal pattern to the semiconductor devices; outputting an expectation value signal pattern, which is expected to be output from the semiconductor device when the input signal pattern is applied to the semiconductor device; comparing an output signal patterns, which are output from the plurality of semiconductor devices, and a predetermined value determined based on the expectation value signal pattern; outputting the match signal when the output signal patterns matches the predetermined value; outputting a match-fail signal when the output signal pattern output from the semiconductor device does not match the predetermined value; storing the match-fail signal; and outputting a first stop signal for stopping an application of the input signal pattern to the semiconductor devices identified by the stored match-fail signal.
The outputting the first stop signal may further output a second stop signal that stops application of the input signal pattern to said semiconductor devices when said output signal patterns matches said predetermined value. The semiconductor device testing apparatus may further comprise: formatting and outputting said input signal pattern to the semiconductor device except when receiving the first stop signal or the second stop signal.
The formatting and outputting may output the input signal pattern except when receiving the first stop signal until the end of the test. The outputting the second stop signal may output the second stop signal during a predetermined cycle; and the outputting the input signal pattern may output the input signal pattern after the end of the predetermined cycle.
According to the fourth aspect of the present invention, a method for testing a semiconductor device for testing a plurality of semiconductor devices, comprises: a step of applying an input signal pattern to each of the plurality of semiconductor devices; a step of stopping for applying the input signal pattern to the semiconductor devices that output an active match signal, the match signal becomes active when an output signal pattern output from the semiconductor device matches a predetermined value; and a step for restarting for applying the input signal pattern only to the semiconductor devices that output the active match signal.
The step of stopping may further stop applying the input signal pattern to the plurality of semiconductor devices except the semiconductor device to which the application of the input signal pattern is restarted by the restarting. The step of stopping may stop applying the input signal pattern to the semiconductor devices that output the active match signal during a predetermined cycle; and the step of restarting may restart the application of the input signal pattern to the semiconductor devices after the end of the predetermined cycle.
The step of stopping may further stop applying the input signal pattern to the plurality of semiconductor devices except the semiconductor devices to which the application of the input signal pattern is restarted until the end of the test.
The method may further comprise: generating an input signal pattern that is to be input to the plurality of semiconductor devices, and an expectation value signal pattern that is expected to be output from the plurality of semiconductor devices when the input signal pattern is applied to the semiconductor device; and comparing a plurality of the output signal patterns output from the plurality of semiconductor devices and the predetermined value determined based on the expectation value signal pattern and outputs the active match signal when the output signal pattern matches the predetermined value.
The method may further comprise: a step of formatting a waveform of the input signal pattern; and a step of outputting the formatted input signal pattern to the semiconductor device; wherein: the step of formatting includes: a step of stopping for outputting at least a part of the input signal pattern to the semiconductor device that outputs the active match signal; a step of restarting for outputting the input signal pattern only to the semiconductor devices that output the active match signal; and a step of stopping for applying the input signal pattern to the plurality of semiconductor devices except the semiconductor device to which the application of the input signal pattern is restarted.
The step of stopping may output a first stop signal that stops applying the input signal pattern to the semiconductor devices that outputs the active match signal. The step of stopping may further output a second stop signal that stops applying the input signal pattern to the semiconductor devices except the semiconductor device to which the application of the input signal pattern is restarted by the step of restarting. The step of stopping may further include a step of detecting whether any one of the plurality of semiconductor devices does not output the active match signal during a predetermined cycle.
The step of stopping may further include: a step of storing which of the semiconductor devices do not output the active match signal that is detected by the detecting during the predetermined cycle; and a step of outputting the first stop signal when the semiconductor device outputs the active math signal during the predetermined cycle or when the semiconductor device is stored by the storing. The step of outputting the stop signal may further output the second stop signal until the end of the test.
According to the fifth aspect of the present invention, a method for testing a plurality of semiconductor devices, comprises: testing the semiconductor device by applying an input signal pattern repeatedly to the semiconductor device for a predetermined period; and stopping the test of the semiconductor device to which an input signal pattern is written imperfectly while continuing the testing for the semiconductor device to which the input signal pattern is written perfectly.
The summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings.